Examiner: Prof. Dr. Bernhard Hoppe

HOCHSCHULE DARMSTADT h_da
FB EIT, July 9th 2010
Master of Science Course:
Electrical Engineering
Analogue CMOS Circuit Design
Final Examination
Examiner: Prof. Dr. Bernhard Hoppe
Instructions to Candidates:
Reading Time: 10 Minutes
Writing Time: 2 hours
You may use notes, slides, textbooks and logbooks as required!
The 4 questions (the first 3 with 20 marks, question 4 makes
40). The minimum score for passing the examination is 40
marks.
1
SECTION A. Devices
Question A1:
Calculate the small signal parameters gm, gmbs, gds for a PMOSand an NMOS transistor, if the magnitude of the drain current
is 50µA and the magnitude of the source-bulk-voltage is 2V.
Use the parameters from the following table! Width = 1µm,
Length 1µm!
Parameter-Symbol
VT0
K’


2F
NMOS
0.7  0.15
110.0  10%
0.4
0.01 (L=2µm)
0.04 (L=1µm)
0.7
PMOS
Unit
Volts
-0.7  0.15
µA/V²
50.0  10%
0.57
V0.5
0.01 (L = 2µm) 1/V
0.05 (L = 1µm)
0.8
V
2
Question A2:
We have two transistors
D-
D+
ID
G+
ID
+B
vDS
G-
vBS
vGS
-B
vDS
vBS
vGS
+S+
-SNMOS
PMOS
and the following model parameters
Parameter-Symbol
VT0
K’


2F
NMOS
0.7  0.15
110.0  10%
0.4
0.01 (L=2µm)
0.04 (L=1µm)
0.7
PMOS
Unit
Volts
-0.7  0.15
µA/V²
50.0  10%
0.57
V0.5
0.01 (L = 2µm) 1/V
0.05 (L = 1µm)
0.8
V
The W/L-ratios of the transistors are 5µm/1µm. If the drain-,
gate-, source-, and bulk-voltages are 3V, 2V, 0V and 0V respectively for the NMOS device and -3V, -2V, 0V and 0V respectively for the PMOS device, find the drain current. The symbol
K’ is µe,h·Cox. Determine the drain currents!
3
Question A3:
What is the worst case ICMR for VDD = 5V  1V, VSS = 0V, ISS =
100 µA, W1/L1 = W2/L2 = 5, W3/L3 = W4/L4 = 1, L = 1,0µm and
VDS5(sat) = 0,2V. Use the parameters, in order to obtain the
minimum ICM-range.
Parameter-Symbol
VT0
K’


2F
NMOS
0.7  0.15
110.0  10%
0.4
0.01 (L=2µm)
0.04 (L=1µm)
0.7
PMOS
Unit
Volts
-0.7  0.15
µA/V²
50.0  10%
0.57
V0.5
0.01 (L = 2µm) 1/V
0.05 (L = 1µm)
0.8
V
4
5
Section B: Circuits
Question A4
Design a Cascode-Amplifier with the following specifications:
VDD=5V, Pdiss < 1mW A = -50V/V, Voutmax = 4V and Voutmin = 1.5V. The
slew rate for a 10pF load should be 10µV/s or greater!
The
amplifier
consists
of
two
NMOS-devices
in
series
connecting ground with the output node and a PMOS-device as
the load-transistor connecting to the supply voltage (M3).
This transistor is biased with a current mirror (M4) sourcing
the required current from VDD. Find the appropriate resistor
value at the bottom of the PMOS diode connected transistor to
provide IBIAS!
One of the NMOS-transistors (M2) has to be biased to a certain
voltage. This voltage has to be provided by a voltage divider
of two additional transistors not shown in the picture. Both
devices are diode-connected active load transistors (NMOS and
PMOS in series).
Use the following
parameter to 1µm.
parameters
Parameter-Symbol NMOS
VT0
0.7  0.15
K’
110.0  10%
and
set
the
PMOS
-0.7  0.15
50.0  10%
channel
length
Unit
Volts
µA/V²
6


2F
0.4
0.01 (L=2µm)
0.04 (L=1µm)
0.7
0.57
0.01
0.05
0.8
V0.5
(L = 2µm) 1/V
(L = 1µm)
V
Create SPICE-Models for NMOS- and PMOS-Transistors from the
values of the table and verify your design with LT-SPICE!
In case of insufficient performance of the first cut hand
design change the appropriate transistor width until the
design goal is met.
7
Solution
Die Slew Rate braucht 100µA nach der Power-Vorgabe sind 200µA
zulässig. Wir nehmen 150µA.
Die Weite des oberen PMOS ist 6µm
Die Weite des unteren NMOS ist 2,73µm
Die Sättigungsspannung des unteren Transistors VDS1 = 0,8V
Wenn man diesen Betrag von der Voutmin-Spannung abzieht
erhalten wir VDS2sat = 0,7V und W2 = 5,57µm
Die Bias-Spannung an Transistor 2 ist 2,2V.
Diese Spannung kann man mit active loads folgendermaßen
einstellen:
In beiden Transistoren muss der gleiche Strom fließen:
Beim NMOS-Transistor ist VDS = VGS = 2,2V und beim PMOSTransistor ist VDS = VGS = 2,8 V:
(W/L)NK‘N(VGS – VTH)2 = (W/L)PK’P(VGS – VTH)2
(W/L)N110(1,5)2 = (W/L)P50(2,1)2
(W/L)N/(W/L)P = (5/11) (2,1)2(1,5)-2
(W/L)N/(W/L)P = 0,9
Also L = 1µm und WN = 4µm und WP = 4,5µm
Der Stromspiegel der M3 ansteuert muss mit einem Widerstand
gegen Masse so eingestellt werden, dass der Strom von 150µA
auch dann noch fließt, wenn VOUTmax anliegt. Also muss bei 1V
zwischen VDD und Voutmax 1V VGS=VDS vorhanden sein, also die
Overdrivespannung muss auf 0,3V gesetzt werden: Vgs = 1V.
Also ist R = 4V/150µA = 26,67 kOhm
Die Biasspannung an M2 von 2,2V erzeugen wir mit einem
Spannnungsteiler aus einer aktiven PMOS und einer aktiven
NMOS-Last.
*CS-Stage transfer characteristic
Vdd 3 0 DC 5.0V
*Vin 1 0 DC 0V
Vin 1 0 PWL (0 0V, 2U 0V, 2.002U 5V, 6U 5V, 6.002U 0V)
*VGG2 4 0 DC 2.2V
*IBIAS 10 0 DC 150U
RBIAS 10 0 22000
Cl 2 0 10P
MVD1 4 4 3 3 MOSP W = 4.5U L =1U
MVD2 4 4 0 0 MOSN W = 4.0U L = 1U
M3 2 10 3 3 MOSP W = 6U L = 1U
8
M3B 10 10 3 3 MOSP W = 6U L = 1U
M2 2 4 41 0 MOSN W = 5.6U L = 1U
M1 41 1 0 0 MOSN W = 5.73U L = 1U
*Level 1 SPICE Modell
.MODEL MOSN NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=
0.7
.MODEL MOSP PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05
PHI=0.8
*.dc lin Vin 0V 5.0V 0.01V
.TRAN 0.002U 10U
.Plot(V2)
4V in 94ns steigende Eingangsflanke:43 V/µs
4,3V in 275ns fallende Eingangsflanke: 15,6V/µs
9